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OC IPC Designers Council Chapter Meeting Archives
OC IPC Meeting History 2003 to 2017
2017 ARCHIVE
July 19th, 2017

TOPIC #1
Embedded Thin Film Resistors
An update on current Applications and Design

SPEAKER
Bruce Mahler
Vice President
Ohmega Technologies, Inc.
One of the PCB Designer's tools is the use of embedded passives. Embedded passives free up routing area, reduce assembly, improve reliability, improve electrical performance and for some designs, reduce the cost of the assembled board. OhmegaPly is an embedded resistive material that has seen growing use in a variety of electronic systems, including high frequency RF circuits, MEMs sensors and heater elements. This presentation will provide an overview of the Thin Film resistor technology including its production, product offerings and characteristics. Examples of current OhmegaPly designs will be reviewed and will be followed by a discussion of future trends for embedded resistors in PCB's.

TOPIC #2
Improving Power Delivery Networks (PDNs) Using Polyimide-based Thin Laminates

What PCB Designers need to know about Buried Capacitance

SPEAKER
Jim-Hyun Hwang
Applications Development Engineer
DuPont
This presentation will provide an overview of the use of thin laminate products (i.e. buried capacitance - a pair of power/ground layer pairs) designed for the power distribution design options. The presentation will discuss the use of both 1-mil and 0.5-mil dielectric laminates and the benefits of each. Buried capacitance layers can reduce the number of decoupling capacitors, free up design space, reduce noise and create higher reliability, along with many other benefits. Example stack-ups from high layer count PCBs used for server and telecommunications equipment will be shared. Also, process challenges at fabricators will be addressed.

April 19th, 2017

TOPIC #1
High Speed DDR4 Memory Design and Power Integrity Analysis

What designers need to know to achieve the best performance with DDR4

SPEAKER
Cuong Nguyen
Field Applications Engineering Manager
EDA Direct

PRESENTATION
DDR4 is an entirely new memory architecture with higher bandwidth, lower power consumption, and higher memory capacity. Incorporating DDR4 memory interfaces in today’s design poses many challenges for both the EE’s as well as the layout engineers. These high speed interfaces require careful considerations in terms of optimizing the electrical signaling between sensitive components and to minimize the noise from high switching activities from the memory devices. Layout constraints must be carefully specified to ensure tight timing alignment for clock and strobe signals. In addition, the Power Distribution Network (PDN) also became more fractured to support the many supplies required by current ASIC and FPGA devices. This, an insufficient decoupling for the supplies, can potentially create more noise, crosstalk, and increase the Electro Magnetic Interference (EMI) in the system.

In this seminar, we will review the DDR4 architecture, routing topologies, signaling protocols, how it can be simulated on the PCB, and how to maximize PDN designs from a layout perspective. Based on the simulation results, optimizing trace routing, board stackup, component placements, connectors, terminations, as well as other tradeoffs can be implemented to maximize the performance of your design.

TOPIC #2
Better PCB Design using the Fabricator’s View

What designers need to know about DFM verification and its impact on your design

SPEAKER
Ammar Abusham
Senior Applications Engineer
Mentor Graphics

PRESENTATION
You are an experienced PCB Designer using a good CAD flow. So why is it that what appears to be a good design to you and your layout tool, always seems to raise a bunch of questions with your fabricator?

Well, the fabricator sees things differently than you. If you’re like most designers, you are very focused on designing a PCB to the electrical and form-factor specifications. And of course, you take pride in how clean your design looks. Your fabricator on the other hand, is mostly paying attention to those aspects of your design which affect yield, costs, and delivery. To avoid any unpleasant surprises in these areas, it might make sense to put yourself in your fabricator’s shoes for a moment and see some of the checking they will perform on your design data prior to committing it to fabrication. To do this, we’re going to step through a typical PCB fabrication process and identify where Design for Manufacturability (DFM) issues are likely to show up and what the fabricator is looking for.

February 8th, 2017

TOPIC
Advanced PCB Laminate Material Selection
What a designer needs to know about choosing the right material for your design


SPEAKER
#1
Michael Gay
Director, High Performance Products
Isola Laminate Group


PRESENTATION
Designers are faced with many choices when trying to select the correct laminate type for your design. Many factors for performance, signal integrity, temperature range, microvia performance and cost come into play. Our speaker will share with us the various materials, properties and electrical characteristics to meet the requirements for your applications.

The presentation will cover various glass fabric and weave styles, resin technologies, pre-preg types, copper foil types and treatment properties. Also, he will discuss the many factors that influence the performance and signal integrity for high speed design applications. Other important information such as laminate thermal performance, guidance for understanding Data Sheet laminate properties, electrical properties and laminate cost considerations will be presented to increase your knowledge and stimulate your questions for our expert speaker.

SPEAKER #2
Dan Diesel
Chief Information Officer and Business Strategist
Insulectro

PRESENTATION
Designers are also faced with selecting the correct laminate type based on the material availability and the need for speed of delivery for the program. Our 2nd speaker will share what is being done in the market to continue to drive faster delivery speed and providing information to the designer regarding material availability and lead times.

2016 ARCHIVE
September 1st, 2016
TOPIC
Flex and Rigid Flex Overview and Design Considerations
What a designer needs to know in order to get the most out of this technology


SPEAKER

John Stine
VP of Operations
KCA Electronics - Anaheim

PRESENTATION
Designers face project requirements for densely populated electronic circuits including pressures to reduce manufacturing times and costs. Design teams are increasingly turning to 3D rigid-flex circuits to meet their project's performance and production requirements. Our speaker will share with us the importance of closer collaboration between the designer and fabricator than traditional board-and-cable designs.

The presentation will share the trade-offs required to produce a successful flex or rigid-flex design to establish a set of design rules the designer can develop with the fabricator's input. These considerations include the number of layers in the design, materials selections, recommended sizes for traces and vias, adhesion methods, and dimensional control. The processes used fabricate flex and rigid flex boards will be highlighted.
June 15th, 2016
TOPIC
Printed Circuit Board Cost Adders
A discussion of factors that drive PCB cost which should be considered early in the design phase to save your company $$$.


SPEAKER

Julie Ellis
Field Applications Engineer
TTM Technologies, Inc.


PRESENTATION
Printed Circuit Board Cost Adders
A designer is faced with many challenges when planning your layout to achieve a balance of performance, quality and reliability versus cost. In this presentation, Julie will discuss the many factors that contribute to cost and explore the trade-off considerations for design optimization. She will explore panel utilization, layer count, material selection, via structure choices, via-filling options, the impact of various sequential laminations, plating processes, surface finishes, scoring, milling and back drilling. You will learn various "rules of thumb" to help you make better choices for mitigating the cost of the boards you design.
March 2nd, 2016
TOPIC
What PI-DC can tell the PCB Designer
Why DC Power Analysis can be such a valuable tool for designers


SPEAKER

Jeff Loyer
Signal and Power Integrity Product Manager
Altium
Prior to joining Altium, Jeff spent more than 20 years as an engineer at Intel, the last 10 as signal integrity lead for their server divisions. While at Intel, he led work groups which significantly impacted the industry's high-speed PCB design practices, including work on the Fiberweave Effect, copper roughness, environmental effects on insertion loss, and insertion loss control and measurement (inventor of SET2DIL).

PRESENTATION
In his presentation, Jeff will explain how a "PI-DC" (DC analysis) tool can help a designer optimize their PDN (Power Distribution Network) design to avoid common issues such as: inadequate voltage to loads; overheating; inefficient power plane design; too few (or too many) vias, or having them sized wrong; and resonant shapes in power and ground shapes. He will present the fundamentals of PI-DC analysis, how to interpret the results, how/when to take action, how it differs from IPC-2152, and how to use the concept of "squares" to optimize your PDN design. The goal is to equip designers with enough knowledge of PI-DC to allow them to use it to obtain the most efficient PDN design possible.
 
2015 ARCHIVE
December 2015
 
The PCB Design Magazine December 2015 Edition
OC IPC DC is Featured in several articles.
Check out:
Page 10 – Large picture of our March 2015 meeting in Irvine with Tom Hausherr as our speaker.
Page 14 – Picture from our June 2015 meeting at Broadcom with Matt Isaacs & Julie Ellis as our speakers.
Page 18-22 – Article by Judy Warner featuring our Chapter President & Wonderful Leader - Scott McCurdy
Page 30 – Article by Rick Hartley with comments on the networking and educational work that our chapter does.

 
November 18th, 2015
 

TOPIC
PCB Routing Guidelines for Signal Integrity and Power Integrity, too

SPEAKER


Chris Heard
Signal Integrity Engineering Consultant
CSH Consulting, LLC

PRESENTATION
Recommendations to improve high speed performance of any design at any datarate
Our speaker has been deeply involved with Signal and Power Integrity for over 25 years and has a wealth of knowledge to share. Chris’s presentation will cover a list of "Do’s and Don'ts" regarding the most commonly seen routing practices that have big impacts on signal integrity. His presentation will cover the importance and signal integrity impact of drill size, pad size, antipad size, ground plane overhang, transition vias, AC Capacitors, skew compensation, backdrilling, blind vias, narrow versus wide lines and surface versus inner layer routing. Use of industry leading simulation tools will be presented.

In his presentation on Power Integrity, Chris will cover Voltage Drop and impedance response versus frequency for various power plane examples. The impact of various capacitor sizes and placement and the use of buried capacitor layers will be shown and discussed. The interaction and the understanding of these two disciplines are vital to success of the designer in achieving fully optimized designs. Don’t miss this opportunity to learn valuable tips from our expert speaker.

 
 
June 3rd, 2015
TOPIC #1
Anti-Pad Optimization on Via-in-Pad Structures

SPEAKER

Matt Isaacs
Technical Director of the SerDes Device Verifcation Team
Broadcom Corp

PRESENTATION
A case study on the Signal Integrity effects of anti-pad clearance and back-drill stub removal
Today’s high-speed circuits demand careful attention to a vast number of attributes of the PCB. Our speaker explores the relationship of anti-pad size and clearance and has done extensive simulation and testing to categorize capacitance and optimum signal integrity on Via-in-Pad designs. Extensive investigation was performed on back-drilling parameters to achieve optimum results at various back-drill stub length removal. Studies investigate the results from back-drill offset. Matt will share the results of this methodology of the extensive simulation and testing which brought excellent results to improve Broadcom’s designs.

TOPIC #2
PCB Enabling Technologies

SPEAKER
Julie Ellis
Field Applications Engineer
Viasystems Technologies Corp


PRESENTATION
Learn the challenges and solutions of printed circuit board designs and fabrication driven by component miniaturization

Faced with a converging set of design requirements, next generation printed circuits will not only see an increase in density, but they will be driven by power, speed, and thermal dissipation. This presentation examines critical printed circuit technologies that will be required for future systems. The session starts with an overview of advanced HDI via structures, as well as next generation buildup technologies essential for chip scale components. The session will conclude with an examination of thermal management techniques such as enhanced thermal vias and heavy copper.
 
 
March 11th, 2015
TOPIC
PCB Design Optimization Starts in the CAD Library
Learn the Benefits of CAD Library Optimization and IPC-7351 Rev C Updates

SPEAKER
Tom Hausherr, CID+
President
PCB Libraries, Inc.


PRESENTATION

Never Build Another CAD Library Part From Scratch Again
Tom shared the latest information on the new IPC-7351 Rev C Land Pattern standard, which contains many changes and improvements. We also learned about a new tool which uses new revolutionary technology to auto-generate Footprint libraries and 3D STEP models from component dimensions and your personal preferences in minutes, which could shave days or even weeks off your PCB layout.
Tom believes that this is the ultimate solution for PCB library automation and organization of library data. He showed us a live demo of their latest, about to be released version of their Library Expert software which will allow you to twist and shape in any direction to get the results you want for customized footprints. With millions of mfr. part numbers readily available for download and Request-a-Part with same day turnaround, you can actually start part placement the same day the EE engineer gives you the Schematic, Bill of Material and Netlist.
Attendees who brought a USB flash drive received the latest release of PCB Libraries V2015.09 Library Expert Lite (LE Lite) for free. The LE Lite has access to every IPC-7351C standard component land pattern calculator and outputs to 21 different CAD tools.
 
 
2014 ARCHIVE
October 9th, 2014

TOPIC
Embedded Passives
Learn the benefits of designing with internal resistors and capacitors

SPEAKER
Bob Carter
Director of Business Development & Technology
Oak-Mitsui Technologies


PRESENTATION

Embedded Capacitance and Improved Power Delivery
This presentation provides an overview/definition of the different types of embedded capacitance as well as fundamentals of power distribution network design for high-speed digital circuits. Bob will also cover how it is used in various types of practical applications such as MEM's and RF modules. Using ultra-thin power and ground plane pairs as embedded capacitance layers provide superb electrical performance with regards to charge delivery. There are particular benefits for reducing or mitigating noise and improving logic transitions. Performance, manufacturability, reliability and cost analysis will be discussed.

SPEAKER

David Burgess,
President
Ticer Technologies

PRESENTATION
Designing with TCR® Thin-Film Embedded Resistor Foil
David Burgess will present an overview of thin-film embedded resistors and educate us on the applications showing the advantages and reliability by designing with this technology. We will learn about power handling of embedded resistors to aid in thermal management. Improvements in signal integrity can be achieved and embedded resistors can eliminate many surface mounted components to free up surface space while improving performance and reliability. Designers will learn about the various types of designs which can greatly benefit from adopting embedded resistor technology.
 
 
June 25th, 2014

TOPIC
Routing Solutions
Strategies, Tools, and Techniques for Speeding up your Connections

SPEAKERS
Terri Kleekamp, CID

Applications Engineering Manager
Mentor Graphics

Xpedition Routing Technology Drives Strategy
Terri Kleekamp and Vern Wnek will introduce and demonstrate the routing strategies of Mentor’s Xpedition™ xPCB Layout, formerly known as Expedition PCB. Much more than just a name change, Terri will share with us Xpedition’s auto-assisted interactive routing technology and put it through its paces. Designers have always taken great pride in planning their designs, combining the needs of the engineers and manufacturers, into what we refer to as “artwork”. Xpedition now boasts a set of highly integrated automated routing features including the Sketch Router™, Hug Router, Real Trace Routing, and Dynamove. These tools facilitate an automated routing experience that includes intuitive user control, high quality, and exceptional performance in the hands of a designer.

John Carney

Staff Application Engineer
Cadence
Allegro Auto Interactive
John Carney from Cadence will be presenting their “Plan-Route-Optimize” strategies for routing in their Allegro tool. John will share their Route Planning tool which offers a fast and easy way to plan the routing of your design. He will share Auto-Interactive Breakout technology and demonstrate Allegro’s Auto Interactive routing features which include Auto-Interactive Delay tuning, phase tuning and Scribble mode routing, which allows you to ‘scribble’ a route path onto the canvas with one click the etch solution is generated. He will share Timing Vision, an innovative environment that allows you to graphically see real-time delay and phase information right on the routing canvas. Coupled with Auto-interactive Phase Tuning and Auto-interactive Delay Tuning capabilities, all of these routines improves the user experience and dramatically shortens the time required to develop a high-quality and effective routing solution.

Yan Killy, CID

Technical Marketing Engineer
PADS
PADS VX
Yan Killy will talk about Mentor Graphics continued investment in all routing technologies available in a PADS design flow. PADS continues to be the leader in Desk Top environment, delivering features and solutions to the PCB design community to solve ever challenging design task. Yan will talk about routing strategies and stage routing and present improvements in Constraint Management, Integrated Project and many other new technologies that help with the routing challenges engineers face. PADS interactive High Speed routing allows designers route critical nets to the rules specified. PADS Autorouting is a productivity enhancing tool, to finish simple and complex designs in fraction of time it will take to do it manually.

 
March 11th, 2014

TOPIC #1
SPEED MATTERS

SPEAKER
Jim Ryan,
Product Manager
Insulectro


PRESENTATION
Shrink the turnaround time in fab by utilizing Z-axis conductive via paste technology
Insulectro supports the long held belief that SPEED MATTERS. This is true in PCB design as well as manufacturing. High Density Interconnects in PCBs have traditionally been done using electroplating. However, new technologies have pushed advanced design requirements such as; finer pitch BGA density, higher PCB layer counts resulting in greater aspect ratios for drilling and plating, and fine diameter vias. These all contribute to process challenges which can effect yields and open opportunities for new solutions. One of these is Z axis conductive via paste. These pastes are environmentally friendly lead free, highly conductive both electrically and thermally, and sinter at normal PCB laminating temperatures to form a strong intermetallic connection with the layer copper. This enabling technology eliminates through hole plating and many sequential lamination steps. The result - designers can realize more reliable circuit boards delivered quicker than ever.



TOPIC #2

eSurface

SPEAKER
Alex Richardson
VP Strategic Operations
eSurface


PRESENTATION

A new look at additive PCB processing for increasing circuit density and decreasing fab costs
eSurface is a new and disruptive technology that enables fast and efficient processing through an additive PCB fabrication technique. The technology affords greater yields with robust results in fine feature requirements used in HDI / fine pitch BGA applications. Utilizing a true covalent bond with the substrate, the technology meets or exceeds current industry standards. This new green, environment friendly process significantly reduces process steps and variabilities, reducing fabrication cycle times and improves cost structures. As finer features, creative high layer stack ups and board density seem to have pushed the print and etch capability threshold, eSurface opens new doors to volumetric efficiency and designs not currently feasible.

 
 
2013 ARCHIVE
AUGUST 12th, 2013
TOPIC
How Your Choice of Components Drive Design, Materials and Manufacturing

SPEAKER

Greg Halvorson
President & CTO of Streamline Circuits


PRESENTATION
How Your Choice of Components Drive Design, Materials and Manufacturing
The evolution of PCB packaging technology poses increasing demands on both the Designer and manufacturer. Greg Halvorson has been fabricating PCB’s for 31 years and continues to push the limits of the technology to meet these ongoing challenges. Greg’s presentation will provide some insight on how the components you select are starting to dictate critical attributes for manufacturing. In design, we have to work together as a team in order to insure the correct copper weights and dielectrics are chosen to optimize signal integrity, loss, and propagation delay. With HDI being so prevalent in the industry today, compromises must take place in your choice of material and other processes. Design attributes such as line width and air gap are just two of the attributes which influence the choice of copper weights.

Combinations of laser drilling and mechanical drilling require the fabricator to make heavy investment in high technology equipment not previously available in order to yield reliable product. Plating processes have also been enhanced in many ways for 28 to 1 aspect Ratios, etc. PCB technology continues to evolve and our industry requires constant updating of software and hardware to maintain supply of high quality, advanced product to the customer. Greg will share many critical attributes and detail some of the industry solutions to enhance your knowledge as a designer of today’s technology and give you a peek at tomorrow from the fabricators point of view.
 
 
APRIL 30th, 2013
TOPIC
What a designer needs to know about making the transition to higher density designs

SPEAKER
Don Carron, CID
Director of Technology - Advanced Circuits



PRESENTATION
Highly Reliable HDI
As modern silicon chips and microprocessor design is getting ever smaller and with tighter pad/pin pitch, the need to incorporate these device footprints into the PCB layout may be daunting for those that have not used them yet. And that, compounded with the discontinuation and end of life of legacy packages are rapidly pushing designers to use these new and very small devices.

Don presented the best way and easy to understand “do’s and don’ts” when considering fine pitch BGAs and small components for your design and board layout. He suggested the best ways to keep costs down and reliability high with robust design elements. The best way to incorporate blind and buried vias structures, as well as via-in-pad with both mechanically-drilled and epoxy-filled vias and the newest HDI using laser microvias, copper filled and staggered or stacked structures were all presented. All with a focus on reliability, this was a highly interesting and informative presentation for PCB designers and engineers of all levels.



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