Calendar of Events
PCB Design Conference
or the link above for more details
The Date! Spread the Word!
Wednesday, November 8th,
8:30am to 5pm
Tustin Community Center @ The Market Place
2961 El Camino Real | Tustin, CA 92782
Educational Event will include
breakfast & lunch, 8 presentations, raffles, sponsor tables, and
Tickets for the Event can be purchased here:
Lunch 'n Learn meeting details coming soon...
Tuesday, September 26th, 2017
Lunch served 11:30 - 11:50
Misc. Business 11:50 - 12:00
Presentation 12:00 - 1:20
Q & A discussion 1:20 - 1:25
Door prize raffle 1:25 - 1:30
Harvard Community Park
14701 Harvard Ave.
Irvine, CA 92606
An Overview of Several Crucial High Frequency PCB Challenges
What designers need to know to improve
high frequency performance of your design
Technical Marketing Manager
PCBs which are used in high frequency or
high speed digital applications have many different variables which
can alter the intended performance of the circuit. Some of these variables
are related to the high frequency circuit materials, some variables
are associated with the circuit design and other variables can be attributed
to the PCB fabrication process. Additionally there are interactions
between these variables and if the designer is aware of these potential
differences, many concerns for PCB electrical performance can be minimized.
will start with an overview of key properties for high frequency laminates,
as well as some properties which are less well-known and can be problematic
if ignored. Following, will be an overview of insertion loss and many
different influences which can impact insertion loss. Some influences
are related to the high frequency circuit material, such as dissipation
factor and copper surface roughness. The circuit design also plays a
role on influencing insertion loss and the impact of final plated finishes
on insertion loss will be discussed. Finally impedance will be discussed,
with a definition of the hierarchy of the variables that influence impedance.
Additionally some examples will be given about how to design signal
transition vias with minimal reflections and showing that conductor
routing may or may not have much influence on impedance reflections
depending on rise times.
Please RSVP no later than noon on Monday, Septembert 25th, 2017
By Clicking the Reservation Link Below
E-Mail RSVP to: email@example.com
Reserve a Spot on your Calendar for Tuesday, September 26th
from 11:30 am to 1:30 pm.
Don't miss out on this educational Lunch n Learn event!
Hope you can attend!